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A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing

Kuehnle, M.; Huebner, M.; Becker, J. [u.a.]

Reconfigurable computing holds the promise of delivering ASIC-like performance while preserving run-time flexibility of processors. In many application domains, the use of FPGAs is limited by area, power, and timing overheads. Coarse-Grained Reconfigurable Architectures offer higher
computation density, but at the price of rather being domain specific. Programmability is also a major issue related to all of the described solutions. This paper describes a heterogeneous multi-core system-on-chip that exploits different flavours of reconfigurable computing, merged together in a high parallel on-chip and off-chip interconnect utilized for both data and
configuration. The aim of this work is to deliver a single monolithic engine that capitalizes on the strong points of different reconfigurable fabrics, while providing a friendly programming interface. The user is ultimately able to manage a broad spectrum of different applications, exploiting the most
efficient means of computation through utilization of each kernel, while retaining a software-oriented development environment as much as possible.

Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2009
Sprache Englisch
Identifikator ISBN: 978-1-4244-4465-6
KITopen-ID: 1000014272
Erschienen in International Symposium on System-on-Chip (SOC 2009), October 5-7, 2009, Tampere, Finland
Verlag IEEE, Piscataway (NJ)
Seiten 106 - 109
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