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Efficient processor instruction set extension by asynchronous reconfigurable datapath integration

Becker, J.; Thomas, A.; Scheer, M.

Abstract: Nowadays, the datapaths of modern microprocessors reach their limits by using static instruction sets. A way out of this limitations is a dynamic reconfigurable processor datapath extension achieved by integrating traditional static datapaths with the coarse-grain dynamic reconfigurable XPP-architecture (extreme processing platform). Therefore, a loosely asynchronous coupling mechanism of the corresponding datapath units has been developed and integrated onto a CMOS 0.13 ÎŒm in standard cell technology from UMC. Here the SPARC compatible LEON processor is used, whereas its static pipelined instruction datapath has been extended to be configured and personalized for specific applications. This allows a various and efficient use, e.g. in streaming application domains like MPEG-4, digital filters, mobile communication modulation, etc. The chosen coupling technique allows asynchronous concurrency of the additionally configured compound instructions, which are integrated into the programming and compilation environment of the LEON processor.

Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2003
Sprache Englisch
Identifikator ISBN: 0-7695-2009-X
KITopen ID: 1000014278
Erschienen in Proceedings / 16th Symposium on Integrated Circuits and Systems Design (SBCCI 2003),September 8 - 11, 2003, Sao Paulo, Brazil
Verlag IEEE Computer Society, Los Alamitos (Calif.)
Seiten 237 - 242
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