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An industrial/academic configurable system-on-chip project (CSoC): coarse-grain XPP-/Leon-based architecture integration

Becker, J.; Thomas, A.; Vorbach, M.; Baumgarte, V.

Abstract: Summary form only given. This paper describes the actual status and results of a dynamically Configurable System-on-Chip (CSoC) integration, consisting of a SPARC-compatible Leon processor-core, a commercial coarse-grain XPP-array of suitable size from PACT Informationstechnologie AG, and application-tailored global/local memory topology with efficient Amba-based communication interfaces. The given adaptive architecture is synthesized within an industrial/academic SoC project onto 0.18 and 0.13 ÎŒm UMC CMOS technologies at Universitaet Karlsruhe (TH). Due to exponential increasing CMOS mask costs, essential aspects for the industry are now adaptivity of SoCs, which can be realized by integrating reconfigurable re-usable hardware parts on different granularities into Configurable Systems-on-Chip (CSoCS).


Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2003
Sprache Englisch
Identifikator ISBN: 0-7695-1870-2
KITopen ID: 1000014281
Erschienen in Proceedings / Design, Automation and Test in Europe Conference and Exhibition (DATE 03), March 3 - 7, 2003, Munich, Germany. Ed.: N. Wehn
Verlag IEEE Computer Soc., Los Alamitos (Calif.)
Seiten 1120 - 1121
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