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Energy efficient NoC for best effort communication

Wolkotte, P. T.; Smit, G. J. M.; Becker, J.

Abstract:
A Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for Multi-Processor System-on-Chip (MPSoC) architectures. In an earlier paper we proposed a energy-efficient reconfigurable circuit-switched NoC to reduce the energy consumption compared to a packet-switched NoC. In this paper we investigate a chordal slotted ring and a bus architecture that can be used to handle the best-effort traffic in the system and configure the circuit-switched network. Both architectures are compared on their latency behavior and power consumption. At the same clock frequency, the chordal ring has the major benefit of a lower latency and higher throughput. But the bus has a lower overall power consumption at the same frequency. However, if we tune the frequency of the network to meet the throughput requirements of control network, we see that the ring consumes less energy per transported hit.


Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2005
Sprache Englisch
Identifikator ISBN: 0-7803-9362-7
KITopen ID: 1000014287
Erschienen in FPL 2005 - International Conference on Field Programmable Logic and Applications, 24 - 26 Aug. 2005, Tampere, Finland. Ed.: T. Rissa
Verlag IEEE Operations Center, Piscataway (NJ)
Seiten 197 - 202
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