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Energy Model of Networks-on-Chip and a Bus

Wolkotte, P. T.; Smit, G. J. M.; Kavaldjiev, N.; Becker, J. E.; Becker, J.

A network-on-chip (NoC) is an energy-efficient on-chip communication architecture for multi-processor system-on-chip (MPSoC) architectures. In earlier papers we proposed two network-on-chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.

Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2005
Sprache Englisch
Identifikator ISBN: 0-7803-9294-9
KITopen ID: 1000014289
Erschienen in Proceedings / 2005 International Symposium on System-on-Chip, 15 - 17 Nov. 2005, Tampere, Finland. Ed.: J. Nurmi
Verlag IEEE Operations Center, Piscataway (NJ)
Seiten 82 - 85
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