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New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits

Huebner, M.; Schuck, C.; Kuehnle, M.; Becker, J.

Short time-to-market pressure, high cost and risks and power consumption are keywords in development of microelectronic solutions for embedded systems as well as for universal and application tailored processor architectures. Modularity and flexibility while design-time, e.g. for system-on-chip (SoC) component design, is not sufficient if the possibility of run-time reconfiguration of novel architectures has to be considered. Here, exploitation of real-time and on-demand reconfiguration of silicon area personalized on suitable granularities demonstrates high situation adaptivity and perspectives for next generation microelectronics. This paper discusses our implemented, synthesized and tested on-demand and partial reconfiguration approaches for fine-grain (Xilinx Virtex FPGAs) data paths. This includes also very new dynamic and partial reconfiguration for 2D placement and routing adaptation for today's fine-grain Xilinx FPGAs

Seitenaufrufe: 37
seit 06.05.2018
Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2006
Sprache Englisch
Identifikator ISBN: 978-0-7695-2533-4
KITopen-ID: 1000014290
Erschienen in Proceedings / IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, 2 - 3 March 2006, Karlsruhe, Germany
Verlag IEEE Computer Society, Los Alamitos (Calif.)
Seiten 6 S.
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