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A high-level target-precise model for designing reconfigurable HW tasks

Boden, M.; Rulke, S.; Becker, J.

Abstract:
The increasing complexity of embedded digital HW/SW systems, rising chip development and fabrication costs, and a shortened time-to-market require system-level design methods and the use of reconfigurable architectures. Our design method concerns the modelling of a system and its HW tasks at a high abstraction level. Using design patterns and macros, our library-based approach provides a consistent flow from an executable specification to its implementation. These templates ease the efficient application of partially run-time reconfigurable architectures. A case study depicts the high-level modelling of a HW task and its implementation in detail


Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2006
Sprache Englisch
Identifikator ISBN: 1-4244-0054-6
KITopen-ID: 1000014297
Erschienen in IPDPS 2006 - 20th International Parallel and Distributed Processing Symposium, 2006, 25 - 29 April 2006, Rhodes Island, Greece
Verlag IEEE Service Center, Piscataway (NJ)
Seiten 8 S.
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