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Evaluation of a Packet Switching Algorithm for Network on Chip Topologies using a Xilinx Virtex-II FPGA based Rapid Prototyping System

Becker, J. E.; Bieser, C.; Becker, J.; Müller-Glaser, K. D.

Abstract:
Due to the rising complexity of modern chip designs, the connection of the different on-chip IP cores has become an important issue. To establish communication links between computation nodes either wide busses or fast serial data paths - so called networks on chip (NoC) - are necessary, depending on the application and the chip design. In case of the serial links a variety of different algorithms and topologies are cogitable, which have to be evaluated and tested to find the optimal solution for a given problem. To do this, the NoC can be emulated on a hardware platform based on FPGAs to exploit the flexibility for short turn-around-times and achieve nearly real time conditions by accelerating the test process. Our approach presents the combination of a flexible and versatile FPGA-based rapid prototyping system and efficient network on chip (NoC) implementation based on Xilinx Virtex-II FPGAs


Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2006
Sprache Englisch
Identifikator ISBN: 1-424-40496-7
KITopen-ID: 1000014302
Erschienen in 2006 IEEE International Symposium on Industrial Electronics, 9-13 July 2006, Montreal, Quebec, Canada; Vol. 4
Verlag IEEE, Piscataway (NJ)
Seiten 3184 - 3189
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