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A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System Setup

Bieser, C.; Bahlinger, M.; Heinz, M.; Stops, C.; Müller-Glaser, K. D.

Abstract:
In the last years FPGAs have become very important for electronic designs - they are very flexible, provide high configurability and allow short turn around times. Especially for rapid prototyping (RP) another feature plays an important rule: the nearly infinite reprogrammability. However, handling these devices in the engineering process is not an easy issue. Therefore our approach presents an efficient, flexible and versatile FPGA configuration methodology based on partial bitstream merging at design time



Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2006
Sprache Englisch
Identifikator ISBN: 1-424-40312-X
KITopen-ID: 1000014304
Erschienen in FPL 2006 - International Conference on Field Programmable Logic and Applications, 28 - 30 Aug. 2006, Madrid, Spain
Verlag IEEE Operations Center, Piscataway (NJ)
Seiten 1 - 4
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