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Dynamic and Partial FPGA Exploitation

Becker, J.; Huebner, M.; Hettich, G.; Constapel, R.; Eisenmann, J.; Luka, J.

Abstract:
Today's field programmable gate array (FPGA) architectures, like Xilinx's Virtex-II series, enable partial and dynamic run-time self-reconfiguration. This feature allows the substitution of parts of a hardware design implemented on this reconfigurable hardware, and therefore, a system can be adapted to the actual demands of applications running on the chip. Exploiting this possibility enables the development of adaptive hardware for a huge variety of applications. A novel method for communication interfaces using look up table (LUT)-based communication primitives enables an exact separation of reconfigurable parts and a fast and intelligent bus-system. A new adaptive software/hardware reconfigurable system is presented in this paper, using a real application in the automotive domain implemented on a Xilinx Virtex-II 3000 FPGA to present results.


Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Zeitschriftenaufsatz
Jahr 2007
Sprache Englisch
Identifikator ISSN: 0018-9219
KITopen ID: 1000014307
Erschienen in Proceedings of the IEEE
Band 95
Heft 2
Seiten 438 - 452
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