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Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC

Brito, A. V.; Kuehnle, M.; Huebner, M.; Becker, J.; Melcher, E. U. K.

An innovative technique to model and simulate partial and dynamic reconfiguration is presented in this paper Developed from modifications of the SystemC kernel, this technique can either be used at transaction level (TLM) or at register transfer level (RTL). At TLM it allows the modeling and simulation of higher-level hardware and embedded software, while at RTL the dynamic system behavior can be observed at signals level. The provided set of instructions promises a reduction in the design cycle. Compared with traditional strategies, information about dynamic and adaptive behavior will be available in an earlier stage,. An established application from the automotive domain is analyzed and illustrates the potential of the technique at TLM. The acquired results will assist in the choice of the best cost/benefit tradeoff regarding FPGA chip area.

Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2007
Sprache Englisch
Identifikator ISBN: 0-7695-2896-1
KITopen-ID: 1000014309
Erschienen in ISVLSI 2007 - IEEE Computer Society Annual Symposium on VLSI, 9-11 March 2007, Porto Alegre, Brazil
Verlag IEEE Computer Society, Los Alamitos (Calif.)
Seiten 35 - 40
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