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Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements

Morra, C.; Cardoso, J. M. P.; Becker, J.

This paper presents a new and retargetable method to identify patterns of instructions with direct support in coarse-grained processing elements (PEs). The method uses a three-address code SSA (static single assignment) representation of the kernel being mapped and rewriting logic for template matching and algebraic optimizations. This approach is able to identify sets of SSA instructions that can be mapped to different PE complexities available in coarse-grained reconfigurable computing architectures. As a proof of concept, results of the approach with a number of benchmark kernels, as far as coverage of template instructions is concerned, are included.

Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Publikationsjahr 2007
Sprache Englisch
Identifikator ISBN: 1-4244-0910-1
KITopen-ID: 1000014311
Erschienen in IPDPS 2007 - IEEE International Parallel and Distributed Processing Symposium, 26-30 March 2007, Long Beach, CA
Verlag IEEE, Piscataway (NJ)
Seiten 1 - 8
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