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A General Purpose Partially Reconfigurable Processor Simulator (PReProS)

Brito, A. V.; Kuehnle, M.; Melcher, E. U. K.; Becker, J.

An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for dynamic reconfiguration. The presented approach can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level (RTL), if the dynamic system behavior is desired to be observed at signal level. The reconfigurable processor can be easily set to model the desired architecture in a behavioral but reasonable way. An example is presented where a XPP processor is implemented and simulated, executing typical applications. The resulting statistics assist either in the choice of the best cost/benefit configuration area that should be available on chip, or in the choice of the target architecture itself.

Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Publikationsjahr 2007
Sprache Englisch
Identifikator ISBN: 1-4244-0910-1
KITopen-ID: 1000014312
Erschienen in IPDPS 2007 - IEEE International Parallel and Distributed Processing Symposium, 26-30 March 2007, Long Beach, CA
Verlag IEEE, Piscataway (NJ)
Seiten 1-7
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