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Originalveröffentlichung
DOI: 10.1109/MWSCAS.2006.382215

Xilinx Virtex-II FPGA Design Acceleration Using a Novel Merging Methodology for Partial Configuration Bitstreams

Bieser, C.; Müller-Glaser, K. D.

Abstract:
RAM-based FPGAs have become very important for electronic designs in the last years since they are very flexible, provide high configurability and allow short turn around times. Especially in the field of Rapid Prototyping (RP) another feature plays an important rule: their infinite reprogrammability. These features help to create freely modifiable Rapid Prototyping systems, which allow both, changes in the hardware architecture as well as in soft-ware. However, handling the FPGA devices in the engineering process is not an easy issue and typically requires deep knowledge of the circuits themselves, their behavior and programming languages as VHDL or Verilog. Our approach presents the combination of a flexible and versa-tile FPGA-based rapid prototyping system and efficient configuration methodology for Xilinx Virtex-It FPGAs supplemented by an easy to use design support for time saving functional implementation and platform configuration.


Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2006
Sprache Englisch
Identifikator ISBN: 1-424-40172-0
KITopen-ID: 1000014317
Erschienen in MWSCAS 2006 - 49th IEEE International Midwest Symposium on Circuits and Systems, 2006, 6 - 9 Aug. 2006, San Juan, Puerto Rico, Vol. 2. Ed.: G. O. Ducoudray Acevedo
Verlag IEEE Service Center, Piscataway (NJ)
Seiten 89 - 93
Nachgewiesen in Scopus
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