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Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor

Kuehnle, M.; Ries, F.; Huebner, M.; Becker, J. [u.a.]

Reconfigurable architectures and NoC (Network-on-Chip) have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting run-time adaptivity opens a new area of research by considering dynamic reconfiguration. In this paper, we present the architecture and associated development tools of an heterogeneous reconfigurable SoC focusing on the chosen communication infrastructure. The SOC integrates units of various sizes of reconfiguration granularity. The included NoC approach demonstrates the mentioned benefits and scalability for actual and future SoC design. On a reference CMOS090 implementation the described interconnect system works at the system reference frequency of 200 MHZ sustaining the required run-time bandwidth on a set of reference applications, at a price < 10\% in area in power consumption with respect to the overall system.

Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Buchaufsatz
Publikationsjahr 2008
Sprache Englisch
Identifikator ISBN: 978-3-9810801-3-1
KITopen-ID: 1000014328
Erschienen in DATE 2008 - Design, automation and test in Europe, 10 - 14 March 2008, Munich, Germany
Verlag IEEE Service Center, Piscataway (NJ)
Seiten 1352 - 1357
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