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Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems

Huebner, M.; Braun, L.; Goehringer, D.; Becker, J.

Abstract:
Since the 1990s reusable functional blocks, well known as IP-Cores, were integrated on one silicon die. These systems-on-chip (SoC) used a bus-based system for intermodule communication. Technology and flexibility issues forced to introduce a novel communication system called network-on-chip (NoC). Around 1999 this method was introduced and until then it is investigated by several research groups with the aim to connect different IP-Blocks through an effective, flexible and scalable communication network. Exploiting the flexibility of FPGAs, the run-time adaptivity through run-time reconfiguration, opens a new area of research by considering dynamic and partial reconfiguration. This paper presents an approach for exploiting dynamic and partial reconfiguration with Xilinx Virtex-II FPGAs for a multi-layer network-on-chip and the related techniques for adapting the network while run-time to the requirements of an application.


Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2008
Sprache Englisch
Identifikator ISBN: 978-1-4244-1693-6
KITopen ID: 1000014331
Erschienen in IPDPS 2008 - IEEE International Symposium on Parallel and Distributed Processing, 14 - 18 April 2008, Miami, Florida, USA
Verlag IEEE, Piscataway (NJ)
Seiten 1 - 6
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