Field programmable gate arrays, FPGAs, are increasingly often applied in various industrial applications as well as investigated in different research projects. Due to the possibility for performing parallel computations, this kind of hardware architecture is especially interesting for high-performance applications. Dynamic and partial hardware reconfiguration, which is provided by several FPGA families such as the Xilinx Spartan 3 and Virtex 2/4 families, further increases the flexibility of these architectures. The Spartan 3 family was a less attractive choice for performing dynamic and partial reconfiguration due to the lack of an internal configuration port. However, a virtual internal configuration port, JCAP, has previously been realized by using the external JTAG interface. This paper presents an approach for internal configuration readback for failure detection and task migration by extending the JCAP core functionality. The paper also presents the first results from implementing self-reconfiguration over JCAP.