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Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures

Morra, C.; Cardoso, J. M. P.; Bispo, J.; Becker, J.

Abstract:
Coarse-grained reconfigurable architectures have proven their value as programmable accelerators for general purpose processors. For early evaluation of those architectures, we need an approach able to exploit and retarget different processing elements (PEs) while maintaining the same compilation flow. Bearing in mind those aspects, this paper describes an approach able to map, evaluate and generate reconfigurable architectures based on an array of PEs. We use Rewriting Logic to map computations described by imperative programming languages to the PEs of the target architecture, a VHDL generation step to prototype the architectures being evaluated, and a clock cycle-based simulator to achieve first assessments about the performance of those architectures. In order to show the potential of our approach, we present results of 1D coarse-grained reconfigurable arrays as accelerator softcores implemented in an FPGA, and the effects of different PE's structures and complexities.


Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2008
Sprache Englisch
Identifikator ISBN: 978-1-424-42333-0
KITopen ID: 1000014339
Erschienen in SASP 2008 - IEEE Symposium on Application Specific Processors, 8 - 9 June 2008, Anaheim, CA
Verlag IEEE, Piscataway (NJ)
Seiten 34 - 41
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