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A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput

Claus, C.; Zhang, B.; Stechele, W.; Braun, L.; Huebner, M.; Becker, J.

Dynamic and partial reconfiguration (DPR) is a special feature offered by Xilinx Field Programmable Gate Arrays (FPGAs), giving the designer the ability to reconfigure a certain portion of the FPGA during run-time without influencing the other parts. This feature allows the hardware to be adaptable to any potential situation. For some applications, such as video-based driver assistance, the time needed to exchange a certain portion of the device might be critical. This paper addresses problems, limitations and results of on-chip reconfiguration that enable the user to decide whether DPR is suitable for a certain design prior to its implementation. A method is therefore introduced to calculate the expected reconfiguration throughput and latency. In addition, an IP core is presented that enables fast on-chip DPR close to the maximum achievable speed. Compared to an alternative state-of-the art realization, an increase in speed by a factor of 58 can be obtained.

Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2008
Sprache Englisch
Identifikator ISBN: 978-1-4244-1960-9
KITopen-ID: 1000014345
Erschienen in FPL 2008 - International Conference on Field Programmable Logic and Applications, 8 - 10 September 2008, Heidelberg, Germany. Ed.: U. Kebschull
Verlag IEEE, Piscataway (NJ)
Seiten 535 - 538
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