The Xilinx Virtex FPGA family provides the capability to perform dynamic partial hardware reconfiguration (DPR). This implies that parts of the system can by dynamically reprogrammed while the rest of the system components continue their execution without being interrupted. Such reconfigurable FPGA systems are becoming more and more common for applications that require a high degree of run-time flexibility. One major research task in this area is to decrease the overhead caused by the reconfiguration duration. This can be done by increasing the reconfiguration rate, which means increasing the system performance when performing the reconfiguration. This paper presents an alternative approach which aims at decreasing the influence of the reconfiguration, by carefully dividing the reconfigurable modules according to the specific data graph and to start processing the data while the following parts of the data graph are still being reconfigured. This prevents data from being stalled and waiting for the reconfiguration to complete. The suggested approach is referred to as waveform-like reconfiguration, since the data processing closely follows the reconfiguration process.