The previous chapter described the most significant blocks that compose the Morpheus architecture, and the added value they provide to the overall computation efficiency and/or usability. The present chapter describes the way that the memory hierarchy and the communication means in Morpheus are organized in order to provide to the computational engines the necessary data throughput while retaining ease of programmability. Critical issues are related to the definition of a computation model capable to hide heterogeneity and hardware details while providing a consistent interface to the end user. This model should be complemented by a data storage and movimentation infrastructure that must sustain the bandwidth requirements of the computation units while retaining a sufficient level of programmability to be adapted to all the different data flows defined over the architecture in its lifetime. These two aspects are strictly correlated and their combination represents the signal processor interface toward the end-user. For this reason, in the following, a significant focus will be given to the definition of a consistent computation patt ... mehrern. This pattern should enable the user to confront Morpheus, in its strong heterogeneity, as a single computational core. All design options in the definition of the Memory hierarchy and the interconnect strategy will be then derived as a consequence of the theoretical analysis that underlines the computational model itself.