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DOI: 10.1145/1988932.1988941

Resource-aware programming and simulation of MPSoC architectures through extension of X10

Hannig, Frank; Roloff, Sascha; Snelting, Gregor; Teich, Jürgen; Zwinkau, Andreas

We present a machine-checked formalisation of the Java memory model and connect it to an operational semantics for Java source code and bytecode. This provides the link between sequential semantics and the memory model that has been missing in the literature. Our model extends previous formalisations by dynamic memory allocation, thread spawns and joins, infinite executions, the wait-notify mechanism and thread interruption. We prove the Java data race freedom guarantee for the complete formalisation in a modular way. This work makes the assumptions about the sequential semantics explicit and shows how to discharge them.

Zugehörige Institution(en) am KIT Institut für Programmstrukturen und Datenorganisation (IPD)
Publikationstyp Proceedingsbeitrag
Jahr 2011
Sprache Englisch
Identifikator ISBN: 978-1-4503-0763-5
KITopen-ID: 1000027296
Erschienen in Proceedings of the 14th International Workshop / Software and Compilers for Embedded Systems (SCOPES '11)
Verlag ACM, New York (NY)
Seiten 48-55
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