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Formal Analyses of Usage Control Policies

Pretschner, A.; Rüesch, J.; Schaefer, C.; Walter, T.


We present a machine-checked formalisation of the Java memory model and connect it to an operational semantics for Java source code and bytecode. This provides the link between sequential semantics and the memory model that has been missing in the literature. Our model extends previous formalisations by dynamic memory allocation, thread spawns and joins, infinite executions, the wait-notify mechanism and thread interruption. We prove the Java data race freedom guarantee for the complete formalisation in a modular way. This work makes the assumptions about the sequential semantics explicit and shows how to discharge them.

DOI: 10.1109/ARES.2009.100
Zitationen: 9
Zugehörige Institution(en) am KIT Institut für Programmstrukturen und Datenorganisation (IPD)
Publikationstyp Proceedingsbeitrag
Publikationsjahr 2009
Sprache Englisch
Identifikator ISBN: 978-1-4244-3572-2
KITopen-ID: 1000028577
Erschienen in International Conference on Availability, Reliability, and Security. ARES, Fukuoka, Japan, 16 - 19 March 2009
Verlag Institute of Electrical and Electronics Engineers (IEEE)
Seiten 98-105
Nachgewiesen in Dimensions
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