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Physical Address Decoding in Intel Xeon v3/v4 CPUs: A Supplemental Datasheet

Hillenbrand, Marius


The mapping of the physical address space to actual physical locations in DRAM is a complex multistage process on today's systems. Research in domains such as operating systems and system security would benefit from proper documentation of that address translation, yet publicly available datasheets are often incomplete. To spare others the effort of reverse-engineering, we present our insights about the address decoding stages of the Intel Xeon E5 v3 and v4 processors in this report, including the layout and the addresses of all involved configuration registers, as far as we have become aware of them in our experiments. In addition, we present a novel technique for reverse-engineering of interleaving functions by mapping physically present DRAM multiple times into the physical address space.

Volltext §
DOI: 10.5445/IR/1000073678
Cover der Publikation
Zugehörige Institution(en) am KIT Institut für Technische Informatik (ITEC)
Publikationstyp Forschungsbericht/Preprint
Publikationsdatum 05.09.2017
Sprache Englisch
Identifikator urn:nbn:de:swb:90-736786
KITopen-ID: 1000073678
Verlag Karlsruher Institut für Technologie (KIT)
Umfang 21 S.
Schlagwörter physical address space, DRAM address decoding, channel interleaving, socket interleaving, rank interleaving
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