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A Reconfigurable High-speed Spiral FIR Filter Architecture

Figuli, Shalina Percy Delicia; Figuli, Peter 1; Becker, Jürgen 1
1 Institut für Technik der Informationsverarbeitung (ITIV), Karlsruher Institut für Technologie (KIT)


The need for efficient Finite Impulse Response (FIR) filters in high-speed applications targets Field Programmable Gate Arrays (FPGAs) as an effective and flexible platform for digital implementation. Although FIR filter offer advantages like linear phase characteristic, no feedback loops and good System stability, its convolution nature poises a challenge in parallelization due to data dependency and computational complexity. To resolve this, we propose a novel FPGA-based reconfigurable filter architecture, which processes several data samples in parallel and breaks down data interdependency in a spiral fashion. This generic pipelined-parallel filter is parameterizable in terms of filter order and degree of parallelization. Experimental results show a throughput of 7.2 GSPS with an operating frequency of only 450MHz for a filter length of 11 with 16 parallel inputs.
With parallelization of 4, it is 4.64 times faster than the stateof- the-art solution for a filter length of 16 and a promising 41\% increase in throughput is achieved for a higher order of 61.

DOI: 10.1109/TSP.2017.8076044
Zitationen: 1
Zitationen: 1
Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Publikationsjahr 2017
Sprache Englisch
Identifikator ISBN: 978-1-5090-3983-8
KITopen-ID: 1000078744
Erschienen in Proceedings of the 40th International Conference on Telecommunications and Signal Processing, TSP 2017, Barcelona, Spain, 5th - 7th July 2017
Verlag Institute of Electrical and Electronics Engineers (IEEE)
Seiten 532-537
Bemerkung zur Veröffentlichung Best Paper Award
Vorab online veröffentlicht am 23.10.2017
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