A Generic Reconfigurable Mixed Time and Frequency Domain QAM Transmitter with Forward Error Correction

In the past three decades, Field Programmable Gate Arrays (FPGAs) have emerged to be the backbone of digital signal processing, especially in high-speed communication systems. However, today, these devices are clocked below 1 GHz and improvement in performance stays a big challenge on all abstraction layers, right from system architecture down to physical technology. Far and wide, myriad number of researches are done on methodologies and techniques which can deliver higher throughput with lower operating frequencies. Towards this projected objective, in this paper an efficient Modulation technique like Quadrature Amplitude Modulation (QAM) along with mixed time and frequency domain approach and Forward Error Correction (FEC) technique have been utilized to employ a generic scalable FPGA based QAM transmitter with filter parallelization being executed in mixed domain. The system developed in this paper achieves an effective throughput of 12.8 Gb/s for 256-QAM with 16 parallel inputs having an operating frequency of 201.25 MHz, while a 18.7 Gb/s effective throughput is realized with 32 parallel inputs at 146 MHz. Thereby, it paves down a promising methodology for applications where having higher clock frequencies is a hard Limit