A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems
Stripf, T. 1; Oey, O.
1; Bruckschloegl, T. 1; Koenig, R. 1; Becker, J. 1; Goulas, G.; Alefragis, P.; Voros, N. S.; Potman, J.; Sunesen, K.; Derrien, S.; Sentieys, O.
1 Karlsruher Institut für Technologie (KIT)
1; Bruckschloegl, T. 1; Koenig, R. 1; Becker, J. 1; Goulas, G.; Alefragis, P.; Voros, N. S.; Potman, J.; Sunesen, K.; Derrien, S.; Sentieys, O.1 Karlsruher Institut für Technologie (KIT)
| Zugehörige Institution(en) am KIT | Institut für Technik der Informationsverarbeitung (ITIV) |
| Publikationstyp | Proceedingsbeitrag |
| Publikationsjahr | 2012 |
| Sprache | Englisch |
| Identifikator | ISBN: 978-076954914-9 KITopen-ID: 1000079189 |
| Erschienen in | 2012 IEEE 15th International Conference on Computational Science and Engineering (CSE 2012) : Paphos, Cyprus, 5 - 7 December 2012 ; [held in conjunction with the 10th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2012) and the 6th International Workshop on Ubiquitous Underwater Sensor Networks (UUWSN 2012) ; proceedings] |
| Verlag | Institute of Electrical and Electronics Engineers (IEEE) |
| Seiten | 383-390 |
| Schlagwörter | ADL, ALMA, automated tool chains, code generation, compilation-oriented architecture description language, Data mining, error prone, Estimation, EU FP7 project architecture oriented parallelization, Hardware, high performance embedded multicore systems, interconnecting modules, microarchitecture, Multicore processing, multiprocessing systems, multiprocessor system on chip devices, optimized programs, parallel architectures, parallel processing, platform-specific programming model, processing units, program compilers, reconfigurable architectures, reconfigurable multicore architectures, Scilab, Scilab programming language, simulation-oriented architecture description language, specification languages, system-on-chip, target architectures |
| Nachgewiesen in | Scopus Dimensions |