A Novel NoC-Architecture for Fault Tolerance and Power Saving

Networks on chips (NoCs) have become a promising candidate for communication in future many-core architectures. However, manufacturing defects and aging effects are expected to cause permanent errors in future technology nodes, which are targeted by NoC-based architectures. Consequently, fault tolerance concepts are necessary in order to deal with these permanent errors. In this work, we propose a novel approach for fault tolerance in NoC-based architectures. We introduce an additional network layer to take over the duties of defective routers. In contrast to existing approaches, the proposed concept is independent of the routing algorithm and can substitute the bandwidth of defective routers. In addition, we show the potential of the concept for power saving. An ASIC implementation of the proposed design is used for performance and power saving evaluation as well as for overhead analysis.