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DOI: 10.1145/3218603.3218630

Pareto-Optimal Power- and Cache-Aware Task Mapping for Many-Cores with Distributed Shared Last-Level Cache

Rapp, Martin; Pathania, Anuj; Henkel, Jörg

Abstract:
Two factors primarily affect performance of multi-threaded tasks on many-core processors with both shared and physically distributed Last-Level Cache (LLC): the power budget associated with a certain task mapping that aims to guarantee thermally safe operation and the non-uniform LLC access latency of threads running on different cores. Spatially distributing threads across the many-core increases the power budget, but unfortunately also increases the associated LLC latency. On the other side, mapping more threads to cores near the center of the many-core decreases the LLC latency, but unfortunately also decreases the power budget. Consequently, both metrics (LLC latency and power budget) cannot be simultaneously optimal, which leads to a Pareto-optimization that has formerly not been exploited. We are the first to present a run-time task mapping algorithm called PCMap that exploits this trade-off. Our approach results in up to 8.6 % reduction in the average task response time accompanied by a reduction of up to 8.5 % in the energy consumption compared to the state-of-the-art.


Zugehörige Institution(en) am KIT Institut für Technische Informatik (ITEC)
Publikationstyp Proceedingsbeitrag
Jahr 2018
Sprache Englisch
Identifikator ISBN: 978-1-4503-5704-3
KITopen-ID: 1000089363
Erschienen in Proceedings of the 23th ACM/IEEE International Symposium on Low Power Electronics and Design - ISLPED '18, Bellevue, WA, July 23-25, 2018
Veranstaltung 23th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2018), Bellevue, WA, USA, 23.07.2018 – 25.07.2018
Verlag ACM Press, New York, NY
Seiten 1–6
Nachgewiesen in Scopus
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