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NCFET-Aware Voltage Scaling

Salamin, Sami 1; Rapp, Martin ORCID iD icon 1; Amrouch, Hussam 1; Pahwa, G.; Chauhan, Y.; Henkel, Jörg 1
1 Karlsruher Institut für Technologie (KIT)

Abstract:

Negative Capacitance Field-Effect Transistor (NCFET) has recently attracted significant attention. In the NCFET technology with a thick ferroelectric layer, voltage reduction increases the leakage power, rather than decreases, due to the negative Drain-Induced Barrier Lowering (DIBL) effect. This work is the first to demonstrate the far-reaching consequences of such an inverse dependency w.r.t. the existing power management techniques. Moreover, this work is the first to demonstrate that state-of-the-art Dynamic Voltage Scaling (DVS) techniques are sub-optimal for NCFET. Our investigation revealed that the optimal voltage at which the total power is minimized is not necessarily at the point of the minimum voltage required to fulfill the performance constraint (as in traditional DVS). Hence, an NCFET-aware DVS is key for high energy efficiency. In this work, we therefore propose the first NCFET-aware DVS technique that selects the optimal voltage to minimize the power following the dynamics of workloads. Our experimental results of a multi-core system demonstrate that NCFET-aware DVS results in 20% on average, and up to 27% energy saving while still fulfilling the same performance constraint (i.e., no trade-offs) compared to traditional NCFET-unaware DVS techniques.


Postprint §
DOI: 10.5445/IR/1000099156
Veröffentlicht am 28.09.2021
Originalveröffentlichung
DOI: 10.1109/ISLPED.2019.8824802
Scopus
Zitationen: 12
Dimensions
Zitationen: 12
Cover der Publikation
Zugehörige Institution(en) am KIT Institut für Technische Informatik (ITEC)
Publikationstyp Proceedingsbeitrag
Publikationsjahr 2019
Sprache Englisch
Identifikator ISBN: 978-1-72812-954-9
ISSN: 1533-4678
KITopen-ID: 1000099156
Erschienen in 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 29-31 July 2019, Lausanne, Switzerland
Veranstaltung ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2019), Lausanne, Schweiz, 29.07.2019 – 31.07.2019
Verlag Institute of Electrical and Electronics Engineers (IEEE)
Nachgewiesen in Dimensions
Scopus
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