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High-Performance Energy-Efficient and Reliable Design of Spin-Transfer Torque Magnetic Memory

Sayed, Nour

In this dissertation new computing paradigms, architectures and design philosophy are proposed and evaluated for adopting the STT-MRAM technology as highly reliable, energy efficient and fast memory. For this purpose, a novel cross-layer framework from the cell-level all the way up to the system- and application-level has been developed. In these framework, the reliability issues are modeled accurately with appropriate fault models at different abstraction levels in order to analyze the overall failure rates of the entire memory and its Mean Time To Failure (MTTF) along with considering the temperature and process variation effects. Design-time, compile-time and run-time solutions have been provided to address the challenges associated with STT-MRAM. The effectiveness of the proposed solutions is demonstrated in extensive experiments that show significant improvements in comparison to state-of-the-art solutions, i.e. lower-power, higher-performance and more reliable STT-MRAM design.

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Volltext §
DOI: 10.5445/IR/1000117747
Veröffentlicht am 24.03.2020
Cover der Publikation
Zugehörige Institution(en) am KIT Institut für Technische Informatik (ITEC)
Publikationstyp Hochschulschrift
Publikationsdatum 24.03.2020
Sprache Englisch
Identifikator KITopen-ID: 1000117747
Verlag KIT, Karlsruhe
Umfang XXIV, 142 S.
Art der Arbeit Dissertation
Fakultät Fakultät für Informatik (INFORMATIK)
Institut Institut für Technische Informatik (ITEC)
Prüfungsdatum 19.07.2019
Referent/Betreuer Prof. M. B. Tahoori
Schlagwörter Computer systems organization, Non-volatile memory, Cache architecture, Low power design, Spin Transfer Torque, Spintronics, Performance, Reliability, Error correcting code, Process variation, Temperature
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