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Energy Optimization in NCFET-based Processors

Salamin, Sami 1; Rapp, Martin ORCID iD icon 1; Amrouch, Hussam 1; Gerstlauer, Andreas; Henkel, Jörg 1
1 Karlsruher Institut für Technologie (KIT)


Energy consumption is a key optimization goal for all modern processors. Negative Capacitance Field-Effect Transistors (NCFETs) are a leading emerging technology that promises outstanding performance in addition to better energy efficiency. Thickness of the additional ferroelectric layer, frequency, and voltage are the key parameters in NCFET technology that impact the power and frequency of processors. However, their joint impact on energy optimization has not been investigated yet.In this work, we are the first to demonstrate that conventional (i.e., NCFET-unaware) dynamic voltage/frequency scaling (DVFS) techniques to minimize energy are sub-optimal when applied to NCFET-based processors. We further demonstrate that state-of-the-art NCFET-aware voltage scaling for power minimization is also sub-optimal when it comes to energy. This work provides the first NCFET-aware DVFS technique that optimizes the processor's energy through optimal runtime frequency/voltage selection. In NCFETs, energy-optimal frequency and voltage are dependent on the workload and technology parameters. Our NCFET-aware DVFS technique considers these effects to perform optimal voltage/frequency selection at runtime depending on workload characteristics. ... mehr

Postprint §
DOI: 10.5445/IR/1000125048
Veröffentlicht am 28.09.2021
DOI: 10.23919/DATE48585.2020.9116301
Zitationen: 4
Zitationen: 4
Cover der Publikation
Zugehörige Institution(en) am KIT Institut für Technische Informatik (ITEC)
Publikationstyp Proceedingsbeitrag
Publikationsmonat/-jahr 03.2020
Sprache Englisch
Identifikator ISBN: 978-1-7281-4468-9
KITopen-ID: 1000125048
Erschienen in 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, France, 9-13 March 2020
Verlag Institute of Electrical and Electronics Engineers (IEEE)
Seiten 630–633
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