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Impact of Interface Traps on Negative Capacitance Transistor: Device and Circuit Reliability

Prakash, Om 1; Gupta, Aniket; Pahwa, Girish; Henkel, Jörg 1; Chauhan, Yogesh S.; Amrouch, Hussam
1 Karlsruher Institut für Technologie (KIT)


In this work, we investigate the impact of Si-SiO $_{2}$ interface traps on the performance of negative capacitance transistor, which is a promising emerging technology that aims at achieving a steep sub-threshold slope. Interface traps induced degradation is well known to be one of the major concerns when it comes to reliability. We focus on investigating the impact of different interface trap concentrations on the figures of merit of both the devices and circuits. Our investigation is performed using TCAD models, which are well calibrated against 14nm production quality FinFETs. This allows accurate analysis and modeling of the impact of NC on the electric field across the SiO $_{2}$ layer. Then, the industry compact model of FinFET (BSIM-CMG) is fully calibrated to reproduce TCAD data. In addition, a physics-based NC model is integrated and solved self-consistently within the BSIM-CMG model in which TCAD data of NC-pFinFETs and NC-nFinFETs are also well matched. This allows studying how interface traps induced degradation can impact circuits. Our results demonstrate that the amplified electric field across the SiO $_{2}$ layer within NC-pFinFET due to NC effect leads to a higher interface trap concentration. ... mehr

DOI: 10.1109/JEDS.2020.3022180
Zitationen: 26
Web of Science
Zitationen: 22
Zitationen: 29
Zugehörige Institution(en) am KIT Institut für Technische Informatik (ITEC)
Publikationstyp Zeitschriftenaufsatz
Publikationsjahr 2020
Sprache Englisch
Identifikator ISSN: 2168-6734
KITopen-ID: 1000126659
Erschienen in IEEE journal of the Electron Devices Society
Verlag Institute of Electrical and Electronics Engineers (IEEE)
Band 8
Seiten 1193-1201
Nachgewiesen in Dimensions
Web of Science
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