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On the Critical Role of Ferroelectric Thickness for Negative Capacitance Device-Circuit Interaction

Prakash, Om; Gupta, Aniket; Pahwa, Girish; Chauhan, Yogesh S.; Amrouch, Hussam


This paper demonstrates the critical role that Ferroelectric (FE) layer thickness (tFE) plays in Negative Capacitance (NC) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a 14nm FDSOI technology node, exploring the impact of tFE on the figures of merit of n-type and p-type devices, voltage transfer characteristic (VTC) and noise margin of inverter as well as the speed of buffer circuits. First, we analyze the device electrical parameters (e.g., ION, SS, ION/IOFF and Cgg) by varying tFE up to the maximum level at which hysteresis in the I-V characteristic starts. Then, we analyze the deleterious impact of Negative Differential Resistance (NDR), due to the drain to gate coupling, demonstrating how it imposes an additional constraint limiting the maximum tFE. We show the consequences of NDR effects on the VTC and noise margin of inverter, which are essential components for constructing robust clock trees in any chip. We demonstrate how the considerable increase in the gate’s capacitance due to FE seriously degrades the circuit’s performance imposing further constraints limiting the maximum tFE. ... mehr

Verlagsausgabe §
DOI: 10.5445/IR/1000137760
Veröffentlicht am 23.09.2021
DOI: 10.1109/JEDS.2021.3110486
Zitationen: 1
Zitationen: 2
Cover der Publikation
Zugehörige Institution(en) am KIT Karlsruher Institut für Technologie (KIT)
Publikationstyp Zeitschriftenaufsatz
Publikationsdatum 06.09.2021
Sprache Englisch
Identifikator ISSN: 2168-6734
KITopen-ID: 1000137760
Erschienen in IEEE Journal of the Electron Devices Society
Verlag Institute of Electrical and Electronics Engineers (IEEE)
Band 9
Seiten 1262-1268
Nachgewiesen in Dimensions
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