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An Analytical Model of Configurable Systolic Arrays to find the Best-Fitting Accelerator for a given DNN Workload

Hotfilter, Tim ORCID iD icon 1; Schmidt, Patrick 1; Höfer, Julian ORCID iD icon 1; Kreß, Fabian ORCID iD icon 1; Harbaum, Tanja ORCID iD icon 1; Becker, Jürgen 1
1 Institut für Technik der Informationsverarbeitung (ITIV), Karlsruher Institut für Technologie (KIT)

Abstract:

Since their breakthrough, complexity of Deep Neural Networks (DNNs) is rising steadily. As a result, accelerators for DNNs are now used in many domains. However, designing and configuring an accelerator that meets the requirements of a given application perfectly is a challenging task. In this paper, we therefore present our approach to support the accelerator design process. With an analytical model of a systolic array we can estimate performance, energy consumption and area for each design option. To determine these metrics, usually a cycle accurate simulation is performed, which is a time-consuming task. Hence, the design space has to be restricted heavily. Analytical modelling, however, allows for fast evaluation of a design using a mathematical abstraction of the accelerator. For DNNs, this works especially well since the dataflow and memory accesses have high regularity. To show the correctness of our model, we perform an exemplary realization with the state-of-the-art systolic array generator Gemmini and compare it with a cycle accurate simulation and state-of-the-art modelling tools, showing less than 1% deviation. We also conducted a design space exploration, showing the analytical model’s capabilities to support an accelerator design. ... mehr


Verlagsausgabe §
DOI: 10.5445/IR/1000157889/pub
Veröffentlicht am 24.05.2024
Postprint §
DOI: 10.5445/IR/1000157889
Veröffentlicht am 28.04.2023
Originalveröffentlichung
DOI: 10.1145/3579170.3579258
Scopus
Zitationen: 1
Dimensions
Zitationen: 1
Cover der Publikation
Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Publikationsdatum 17.01.2023
Sprache Englisch
Identifikator ISBN: 979-84-00-70045-3
KITopen-ID: 1000157889
Erschienen in DroneSE and RAPIDO: System Engineering for constrained embedded systems
Veranstaltung HiPEAC Conference (2023), Toulouse, Frankreich, 16.01.2023 – 18.01.2023
Verlag Association for Computing Machinery (ACM)
Seiten 73–78
Nachgewiesen in Scopus
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