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Testing for Multiple Faults in Deep Neural Networks

Moussa, Dina A. 1; Hefenbrock, Michael 2; Tahoori, Mehdi 3
1 Karlsruher Institut für Technologie (KIT)
2 Institut für Telematik (TM), Karlsruher Institut für Technologie (KIT)
3 Institut für Technische Informatik (ITEC), Karlsruher Institut für Technologie (KIT)

Abstract:

Deep Neural Networks (DNNs) implemented on hardware accelerators are vulnerable to various faults. This necessitates the development of efficient testing methodologies to detect them in DNN accelerators. In this work, we propose a test pattern generation approach to detect fault patterns in DNNs’ synaptic weight value representations at a bit level. The experimental results show that the generated test patterns provide 100% fault coverage for targeted fault patterns. Besides, a high compaction ratio was achieved over different datasets and model architectures (up to 50×), and high fault coverage (up to 99.9%) for unseen fault patterns during the test generation phase.


Zugehörige Institution(en) am KIT Institut für Technische Informatik (ITEC)
Institut für Telematik (TM)
Publikationstyp Zeitschriftenaufsatz
Publikationsmonat/-jahr 06.2024
Sprache Englisch
Identifikator ISSN: 2168-2356, 2168-2364
KITopen-ID: 1000169545
Erschienen in IEEE Design and Test
Verlag Institute of Electrical and Electronics Engineers (IEEE)
Band 41
Heft 3
Seiten 47–53
Vorab online veröffentlicht am 13.02.2024
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