Characterization of the radiation tolerant ToASt ASIC for the readout of the PANDA MVD strip detector

The ToASt ASIC is a 64-channel integrated circuit developed for the readout of the Silicon strip detector project designed to be placed in the Micro-Vertex Detector of the PANDA experiment. ToASt is implemented in a commercial 110 nm CMOS technology and can provide information on the position, time, and deposited energy of the particle passing through the detector. Its time resolution is given by its 160 MHz master clock. The ASIC has been developed in the framework of the European FAIRnet project. The chip has been characterized electrically both standalone and coupled with sensors, with focus on its noise performances. It has also been tested for radiation tolerance, both in terms of Total Ionizing Dose and Single Event Upset. In particular, this work aims to guarantee that the studied ASICs can sustain the levels of ionizing radiation expected in the PANDA experiment and to study the noise characteristics for the two polarities of the ASIC.