A Power-Efficient mm-Wave Divide-by-16 Frequency Divider in SiGe BiCMOS Technology

We present the design and characterization of a power-efficient divide-by-16 frequency divider used as prescaler in a D-band radar system. The divider consists of two high-speed emitter-coupled logic (ECL) divide-by-2 stages with split-load for speed enhancement, as well as two static ECL divide-by-2 stages. All divider stages are optimized individually for low power and matched sensitivity. An analysis of the employed split-load, current-scaling, and layout optimization techniques is included in this paper. As proof of concept, the divider was fabricated in a 130-nm SiGe BiCMOS technology. Measurements demonstrate a locking range from 14-106 GHz. The divide-by-16 frequency divider achieves a self-oscillation frequency (SOF) of 86.9 GHz at a remarkably low power consumption of 90 mW including buffers. The first divide-by-2 stage dissipates only 25 mW.