Xihe: A WCET analysis tool for digital signal processors

Static worst-case execution time (WCET) analysis is crucial for designing safety-critical real-time systems, as it provides an upper bound on the execution time of real-time applications on the underlying hardware. While digital signal processors (DSPs) are widely adopted in real-time systems due to their specialized architecture, optimized instruction set, power efficiency, and real-time processing capabilities, existing WCET analyses primarily focus on general-purpose CPU cores, with limited attention given to DSPs. This paper addresses this gap by proposing a WCET analysis tool called Xihe for DSPs. Xihe introduces a timing semantics to precisely model control-flow among instructions and presents novel techniques for constructing the control-flow graph and detecting loop bounds based on these semantics. Additionally, a novel memory access behavior analysis which takes into account the DSP’s instruction-level parallelism execution flow is developed. Experimental evaluation of Xihe using MRTC benchmark programs on the C66x core demonstrates a relatively tight average overestimation of 67% compared to measured results.