Fabrication and FEM Analysis of Flip-Chip Bonded Si Chip-with Au Stud Bumps on Si Interposer

This paper presents fabrication and FEM-based study of flip-chipped Si chip with Si interposer with Au stud bumps for two different cases (periphery-bumped die and Area-array bumped die). The Au stud bump has been made on 1 µm-thick Al pad with 150 µm pitches in Si chip and Si interposer. After quasi-automatic bumping process, the average height of the Au stud bump is measured 37.5 µm and its diameter is around 70 µm, respectively. The two components have been flip-chip bonded at 200 °C for 1 minute. Firstly, the resistance of the bonded Au stud bumps has been measured by using daisy chain and the resistance of each Au stud bump pair is measured 35 mΩ. Secondly, warpage of the Si chip bonded on the Si substrate has been measured with 3D optical profiler. Through comparison between experiment and simulation, it is found that normal stress caused by applying force has a similar distribution as the measured profile of the Si chip for both perimeter bumping and full area bumping.