Diagnostic Test Generation for Fault Localization in Printed Neuromorphic Circuits

Printed electronics (PE) enable lightweight, flexible, and low-cost devices for the Internet of Things (IoT) and wearable applications. Compared to conventional silicon-based electronics, PE trades peak performance for advantages in cost efficiency, mechanical flexibility, and large-area fabrication. However, its manufacturing processes remain unreliable and are prone to structural defects and variation due to inherent limited control in additive manufacturing. Printed neuromorphic circuits (pNCs) leverage the benefits of PE for on-demand analog edge computation in target applications but remain vulnerable to such defects. Diagnostic testing is therefore essential not only for detection but also for localizing faults to specific subcircuits and regions in the layout, a step critical for guiding yield improvement and reducing the cost of downstream inspection. We propose a diagnostic test pattern generation (DTPG) framework for fault localization in pNCs under black-box access. While ATPG is typically formulated as an optimization problem for fault detection, our approach extends this formulation by explicitly optimizing for fault distinguishability. ... mehrOn ten UCI datasets, the framework achieves up to 20.7% higher diagnostic coverage with a reduction of up to 3.6 times the number of undetectable subcircuits than detection-only test sets, while constraining the number of patterns to reduce storage overhead. These results demonstrate effective fault localization and establish a foundation for finer-grained, component-level diagnosis in future work.