MF-ECC: Memory-Free Error Correction for Hyperdimensional Computing Edge Accelerators

Brain-inspired Hyperdimensional Computing (HDC) is emerging as a compelling paradigm for learning at the edge because of its one-shot learning capability, inherent scalability, and exceptionally low computational overhead. While HDC is robust to noise, soft and hard memory faults in the memory components of HDC accelerator can still significantly degrade accuracy. Conventional error correction codes (ECC) are commonly used to mitigate such faults, but their associated overhead make them impractical for resource-constrained edge devices. In this paper, we present a novel memory-free error correction technique to enhance the fault tolerance of HDC systems without requiring any dedicated memory to store check-bits. This way, not only is the memory overhead and its associated constraints eliminated, but also the possibility of errors occurring within the Error-Correcting Code (ECC) check-bits themselves is omitted. Additionally, the proposed method is highly scalable, with minimal hardware overhead, and is therefore suitable for edge implementations. We validate the approach on an FPGA, demonstrating its practicality and effectiveness. Compared to the state-of-the-art correction methods, our memory-free design achieves 27× lower LUT utilization, more than 80× fewer registers and no DSP, BRAM, or latency at all. ... mehrAt the same time, it is capable of preserving inference accuracy under a 12× higher fault possibility.