Algorithm–Technology Co-Optimization for Reliable NVM-CAM Systems

In-memory content addressable memories (CAMs) offer an efficient hardware-based approach to accelerate search operations in data-intensive workloads. Non-volatile memory (NVM)-based CAMs, with their high density, low standby power, and CMOS compatibility, enable energy-efficient realization of large-scale in-memory CAMs. However, resistive nature of NVMs results in unacceptably high search error rate (SeER) (on the order of 10$^{−4}$) coupled with device-level variability. This paper presents an algorithm–technology co-optimization solution to mitigate SeER, by integrating circuit- and software-level error mitigation strategies. To evaluate the approach on realistic workloads, an open-source simulation platform was developed, supporting full-system analysis and NVM-CAM co-design. Experimental results demonstrate a reliable NVM-CAM achieving 0% SeER without hardware overhead, matching the SeER of an ideal NVM-CAM, with only a small increase in runtime and energy of 6% and 4%, respectively.