LOFT: Latent-Fault Optimization Training for Yield Boost in Resistive Crossbar AI Accelerators

Non-volatile memory (NVM) based computation in memory architectures enable energy efficient neural network acceleration by performing matrix vector multiplication directly within memory arrays, thereby eliminating the memory wall bottleneck in AI workloads. However, fabrication of NVM crossbars is prone to defects that introduce permanent faults in memory cells, distort stored model parameters, and degrade the accuracy of inference. Existing mitigation approaches rely on time-consuming post-fabrication fault maps and chip specific retraining or remapping, which incur significant testing, retraining, and deployment overhead. This work proposes the latent-fault optimization training (LOFT) technique that eliminates explicit per chip fault map extraction and improves manufacturing yield. Training is formulated as a latent fault ensemble optimization in which each forward pass samples stochastic fault realizations, allowing the model to learn robustness against hardware induced perturbations. Experimental evaluation across multiple neural network architectures shows that the proposed method significantly improves tolerance to fabrication defects, increasing the effective inference yield by up to 60% without requiring chip-specific retraining.