Spectral Signatures for Parametric Fault Detection in Flexible Electronics

Flexible electronics (FE) based on indium gallium zinc oxide (IGZO) unipolar thin-film transistor (TFT) technologies enable lightweight, conformable systems for wearable sensing, biomedical monitoring, and human-machine interfaces.
These target applications rely on analog and mixed-signal (AMS) processing blocks that must remain accurate despite four key testing challenges: increased device variability and defect rates from low-cost unipolar fabrication; susceptibility to post-manufacturing failures due to the absence of rigid packaging; parametric faults that degrade analog accuracy without hard digital failures; and the high cost and in-field inaccessibility of specialized Automatic Test Equipment (ATE) for low-cost disposable FE systems.
Conventional test approaches relying on analog-to-digital converters (ADCs) incur prohibitive area overhead in resource-constrained systems; critically, ADC accuracy is itself subject to process, voltage, and temperature (PVT) variations, leading to test invalidations.
This work proposes a frequency-domain test signature generation circuit exploiting spectral energy distribution from a voltage-controlled oscillator (VCO) to detect faults and parametric deviations in AMS circuits under test (CUTs).
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The VCO converts fault-induced control-voltage deviations into frequency shifts processed through lightweight analog filters.
Root-mean-square (RMS) values of harmonic components serve as compact signatures exhibiting monotonic sensitivity to operating-point deviations while preserving ordering across PVT corners, ensuring robust operation without precision references or matched comparators.
A ratiometric refinement of this signature is shown to suppress post-calibration drift from temperature and supply variation by up to an order of magnitude, validated through direct monotonicity verification across all evaluated corners and supply voltages.
The signature is readable via two standard I/O pins, enabling in-field test without ATE.
The circuit occupies 6390$\mu$m$^2$ and consumes 16.7$\mu$W, achieving 26$\times$ area reduction versus compact ADCs and nearly 1500$\times$ versus SAR implementations.