Analytical Design of a Numerical Stabilizer for V-ITM Power Hardware-in-the-Loop Applications

Power hardware-in-the-loop (PHIL) simulations enable real-time interaction between numerical models of interest (MOI) and physical hardware under test (HuT), but are prone to numerical oscillations caused by the trapezoidal integration of simulated inductances. These oscillations can lead to voltage overshoots, posing a significant risk to the HuT. This paper introduces a mathematical design methodology for a simulated parallel damping resistor, referred to as a numerical stabilizer, that analytically links the simulation parameters to a desired oscillation attenuation at the voltage-type (V-) ideal transformer model (ITM) interface algorithm (IA) in low-voltage ride through (LVRT) scenarios. This enables the analytical dimensioning of the stabilizer to limit the voltage overshoot to a predefined value without empirical tuning. Experimental validation in a three-phase PHIL setup confirms that the proposed approach effectively reduces the maximum overshoot while maintaining the highest possible PHIL voltage accuracy. Furthermore, a correction factor is introduced to account for real-world deviations, ensuring robust protection of the HuT. ... mehrThe presented method provides an analytical foundation for the systematic stabilization of V-ITM PHIL simulations in LVRT applications.