KIT | KIT-Bibliothek | Impressum | Datenschutz

Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs

Bieser, C.; Mueller-Glaser, K. D.

Abstract:
RAM-based FPGAs have become very important for electronic designs in the last years since they are very flexible, provide high configurability and allow short turn around times. Especially in the field of Rapid Prototyping (RP) another feature plays an important rule: their infinite reprogrammability. These features help to create freely modifiable Rapid Prototyping systems, which allow both, changes in the hardware architecture as well as in software. However, handling the FPGA devices in the engineering process is not an easy issue and typically requires deep knowledge of the circuits themselves, their behavior and programming languages as VHDL or Verilog. Our approach presents the combination of a flexible and versatile FPGA-based rapid prototyping system and efficient configuration methodology for Xilinx Virtex-II FPGAs supplemented by an easy to use design support for time saving functional implementation and platform configuration.


Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Jahr 2006
Sprache Englisch
Identifikator ISBN: 978-0-7695-2580-8
KITopen ID: 1000014295
Erschienen in Proceedings / Seventeenth IEEE International Workshop on Rapid System Prototyping, shortening the path from specification to prototype, 14 - 16 June 2006, Chania, Crete, Greece
Verlag IEEE Computer Society, Los Alamitos (Calif.)
Seiten 193 - 199
KIT – Die Forschungsuniversität in der Helmholtz-Gemeinschaft KITopen Landing Page