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URN: urn:nbn:de:swb:90-211868

RISPP: A Run-time Adaptive Reconfigurable Embedded Processor

Bauer, Lars

This Ph.D. thesis describes a new approach for adaptive processors using a reconfigurable fabric (embedded FPGA) to implement application-specific accelerators. A novel modular Special Instruction composition is presented along with a run-time system that exploits the provided adaptivity. The approach was simulated and prototyped using and FPGA. Comparisons with state-of-the-art appl.-specific and reconf. processors demonstrate significant improvements according the performance and efficiency.

Zugehörige Institution(en) am KIT Institut für Technische Informatik (ITEC)
Publikationstyp Hochschulschrift
Jahr 2009
Sprache Englisch
Identifikator KITopen-ID: 1000021186
Verlag Karlsruhe
Abschlussart Dissertation
Fakultät Fakultät für Informatik (INFORMATIK)
Institut Institut für Technische Informatik (ITEC)
Prüfungsdaten 15.12.2009
Referent/Betreuer Prof. J. Henkel
Schlagworte Reconfigurable Processor, Application Specific Processor, ASIP, Run-time Adaptivity, Run-time System, FPGA,Efficiency, Performance,Special Instruction
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