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Verlagsausgabe
DOI: 10.5445/IR/1000030412
Veröffentlicht am 25.05.2018
Originalveröffentlichung
DOI: 10.1155/2011/121353
Scopus
Zitationen: 16

Operating System for Runtime Reconfigurable Multiprocessor Systems

Goehringer, D.; Huebner, M.; Nguepi Zeutebouo, E.; Becker, J.

Abstract:
Operating systems traditionally handle the task scheduling of one or more application instances on processor-like hardware architectures. RAMPSoC, a novel runtime adaptive multiprocessor System-on-Chip, exploits the dynamic reconfiguration on FPGAs to generate, start and terminate hardware and software tasks. The hardware tasks have to be transferred to the reconfigurable hardware via a configuration access port. The software tasks can be loaded into the local memory of the respective IP core either via the configuration access port or via the on-chip communication infrastructure (e.g. a Network-on-Chip). Recent-series of Xilinx FPGAs, such as Virtex-5, provide two Internal Configuration Access Ports, which cannot be accessed simultaneously. To prevent conflicts, the access to these ports as well as the hardware resource management needs to be controlled, e.g. by a special-purpose operating system running on an embedded processor. For that purpose and to handle the relations between temporally and spatially scheduled operations, the novel approach of an operating system is of high importance. This special purpose operating system, c ... mehr


Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Zeitschriftenaufsatz
Jahr 2011
Sprache Englisch
Identifikator ISSN: 1687-7195, 1687-7209
URN: urn:nbn:de:swb:90-304122
KITopen-ID: 1000030412
Erschienen in International journal of reconfigurable computing
Band 2011
Seiten 121353/1-16
Nachgewiesen in Scopus
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