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DOI: 10.5445/IR/1000049345

DRAM Aware Last-Level-Cache Policies for Multi-core Systems

Hameed, Fazal

Two important parameters for DRAM cache are the miss rate and the hit latency, as they strongly influence the performance. This thesis investigate the latency and miss rate trade-offs when designing a DRAM cache hierarchy. It proposes novel application-aware and DRAM aware policies that simultaneously reduce miss rate (while considering the cache access pattern of concurrently running applications) and hit latency (while considering DRAM characteristics).

Zugehörige Institution(en) am KIT Institut für Technische Informatik (ITEC)
Publikationstyp Hochschulschrift
Jahr 2015
Sprache Englisch
Identifikator URN: urn:nbn:de:swb:90-493452
KITopen-ID: 1000049345
Verlag Karlsruhe
Abschlussart Dissertation
Fakultät Fakultät für Informatik (INFORMATIK)
Institut Institut für Technische Informatik (ITEC)
Prüfungsdaten 06.02.2015
Referent/Betreuer Prof. J. Henkel
Schlagworte Cache, Memory, Computer Architecture, Embedded Systems
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