DRAM Aware Last-Level-Cache Policies for Multi-core Systems

Two important parameters for DRAM cache are the miss rate and the hit latency, as they strongly influence the performance. This thesis investigate the latency and miss rate trade-offs when designing a DRAM cache hierarchy. It proposes novel application-aware and DRAM aware policies that simultaneously reduce miss rate (while considering the cache access pattern of concurrently running applications) and hit latency (while considering DRAM characteristics).